P-N JUNCTION OPTOELECTRONIC DEVICE FOR IONIZATION OF FIELD EFFECT DOPANTS

专利摘要:
An optoelectronic device (100) having a mesa structure (124) comprising: - a first (106) and a second (108) semiconductor portion forming a pn junction, - a first electrode (112) electrically connected to the first portion is disposed between the second portion and the first electrode, the device further comprising: - a second electrode (116) electrically connected to the second portion; - an element (118, 120) capable of ionizing dopants of the pn junction via a generating an electric field in the pn junction and covering at least a portion of the lateral flanks of at least a portion of the first and / or second semiconductor portion located at the pn junction, upper faces the first electrode and the second electrode form a substantially planar continuous surface (122).
公开号:FR3023065A1
申请号:FR1456084
申请日:2014-06-27
公开日:2016-01-01
发明作者:Ivan-Christophe Robin；Hubert Bono
申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
IPC主号:

专利说明:

[0001] TECHNICAL FIELD AND PRIOR ART The invention relates to the field of pn-type optoelectronic devices such as light-emitting diodes (LEDs or LEDs or micro-LEDs), used in particular for the realization of any light device based on LEDs (screens, projectors, image walls, etc.), or photodetector devices such as photodiodes. A light emitting diode emitting blue light generally comprises a GaN-based pin junction comprising: a p-doped GaN layer with typically 1019 acceptors / cm 2, an unintentionally doped, or intrinsic, layer of GaN typically at 1017 donors / cm 2 in which quantum wells of InGaN are formed, and a layer of n doped GaN at 1019 donors / cm '. The unintentionally doped layer comprising the quantum wells in which the light emission occurs is called the active zone. An AIGaN electron blocking layer with an aluminum concentration of between 8% and 15% and p-doped can be added between the active zone and the p-doped GaN layer, as described in the document "The influence of acceptor anneal. temperature on the performance of InGaN / GaN quantum well-light-emitting diodes, JD Thomson et al., Journal of Applied Physics 99, 024507 (2006). This electron blocking layer makes it possible to limit the displacement of electrons from the active zone towards the p-doped GaN layer. The main problem limiting the efficiency of this type of light-emitting diode is the high activation energy of the acceptors in the p-doped GaN layer, which is typically of the order of 200 meV.
[0002] A UV-emitting light emitting diode (UV LED) can be made using AIGaN to form the pin junction, with GaN quantum wells. As the aluminum concentration in AlGaN increases, the activation energy of the acceptors in the p-doped AlGaN increases. For example, this activation energy is of the order of 600 meV in the AIN. The quantity of acceptors activated in the AlGaN is then extremely low, thus limiting the effectiveness of such a UV LED. To reduce the activation energy of the acceptors in this UV LED, p-doped GaN can be used in place of the p-doped AIGaN. This has the disadvantage of limiting the radiative efficiency in the active area of the UV LED is in AIGaN. In addition, a part of the UV light emitted by the active zone is absorbed by the p-doped GaN. In the examples described above, the limitations observed are due to the high activation energy of the acceptors in the p-n junction. It is also possible to encounter similar problems related to a high activation energy of the donors when they are deep. For example, these problems are found in the case of LEDs whose p-n junctions are made of diamond because in this case, the donors have a high ionization energy (of the order of 460 meV).
[0003] In addition, the problems described above are also found analogously for photodiodes, for example those intended to perform a detection of UV light and made from AIGaN or diamond. SUMMARY OF THE INVENTION An object of the present invention is to propose a new type of pn-junction optoelectronic device, for example a light-emitting diode or a photodiode, whose transmission or detection efficiency, or internal quantum efficiency, is improved over prior art junction optoelectronic devices, especially for semiconductor materials having high acceptor or donor activation energies. For this purpose, the present invention proposes an optoelectronic device comprising at least one mena structure comprising at least: a first and a second semiconductor portion, one being p-doped and the other being n-doped, and forming together a pn junction, a first electrode electrically connected to the first semiconductor portion which is disposed between the second semiconductor portion and the first electrode, the optoelectronic device further comprising at least: a second electrode electrically connected to the second portion; semiconductor device, an element capable of ionizing dopants of the pn junction via a generation of an electric field in the pn junction and covering at least a portion of the lateral flanks of at least a part of the first and / or of the second semiconductor portion located at the pn junction, and in which upper faces of at least the first electrode and the second electrode form a substantially flat continuous surface. The presence of the element capable of ionizing dopants of the p-n junction in the vicinity of the doped semiconductor p or n of the optoelectronic device enables the generation of an electric field improving the conductivity of the doped semiconductor p or n. This field effect causes an ionization of the dopants in this semiconductor (ionization of the acceptors for p-doped semiconductor or ionization of the donors for n-doped semiconductor), which makes it possible to increase the internal quantum efficiency, that is to say, the emission or reception efficiency of the optoelectronic device because, for example, a larger number of acceptors (holes) are available to recombine with the donors (electrons) coming from the doped semiconductor n of the device, especially when the semiconductor doped with a high acceptor activation energy, or a larger number of donors are available to recombine with the p-doped semiconductor acceptors, especially when the doped semiconductor a high donor activation energy. The optoelectronic device may advantageously comprise one or more semiconductors having significant acceptor activation energies, for example greater than or equal to approximately 50 meV, such as GaN (whose value of the ionization energy of the acceptors is about 200 meV) and InGaN quantum wells (whose value of the ionization energy varies as a function of the indium concentration and is between about 50 meV and 200 meV), for example for the realization a light-emitting diode emitting a blue-colored light, or AlGaN (whose value of the ionization energy of the acceptors is greater than about 200 meV), or AIN (whose value of the ionization energy of acceptors is equal to about 600 meV), and quantum wells in GaN or AIGaN, for example for producing a light emitting diode emitting a UV light or a photodiodes performing UV light detection. It is also possible that InGaN is used as a p-type semiconductor material for some light-emitting diodes. It is also possible that the optoelectronic device comprises one or more semiconductors having energies of activation of important donors, for example greater than or equal to about 50 meV such as diamond (the value of the ionization energy of donors is approximately 460 meV), for example for producing a light emitting diode or a photodiode operating in the UV range.
[0004] The strong integration of the elements of such an optoelectronic device has the advantage of minimizing the current densities obtained in the electrodes, and therefore of reducing Joule heating in the device.
[0005] The expression "mesa structure" designates the fact that the optoelectronic device is made in the form of a stack of the first and second doped semiconductor portions, a junction zone being present between these two semiconductor portions. doped conductor, and that this stack is etched on at least a portion of its height as an island called mesa and can form pads of any shape having such a stack. In addition, the substantially planar continuous surface formed by at least the upper faces of the electrodes of the device makes it easy to hybridize, for example without using inserts such as connection microbeads, the device to another element, such as an electronic circuit may also include a flat face at which there are similar materials to those of the device, for example by direct bonding. The upper faces of the electrodes form a substantially flat continuous surface, that is to say are arranged substantially in the same plane. The term "substantially planar" is used here to designate the fact that the surface formed by these upper faces may have variations in height, or thickness, between 0 and about 150 nm. The term "p-n junction" as used herein also refers to a p-i-n junction.
[0006] The element capable of ionizing dopants of the pn junction may comprise: at least one dielectric passivation layer covering said at least part of the lateral flanks of at least a portion of the first and / or second portion of semi a conductor located at the junction pn and at least one electrically conductive gate such that the dielectric passivation layer is disposed between the gate and said at least a portion of the first and / or second semiconductor portion, and / or at least one metal portion covering said at least part of the lateral flanks of at least a portion of the first and / or second semiconductor portion located at the pn junction and forming a Schottky contact with said at least a portion of the first and / or second semiconductor portion.
[0007] In this case, the optoelectronic device may be such that: a first portion of the dielectric passivation layer laterally surrounds at least a portion of the first electrode, the first semiconductor portion and at least a portion of the second semi-conductor portion; -conducteur - the gate laterally covers the first part of the dielectric passivation layer - a second portion of the dielectric passivation layer laterally covers the gate (the gate may be arranged between the first and second parts of the passivation layer dielectric), and the second electrode laterally covers the second part of the dielectric passivation layer, or the optoelectronic device may be such that: the metal portion laterally surrounds at least part of the first electrode, the first semiconductor portion; and at least a portion of the second semiconductor portion, and - the the second electrode laterally covers the metal portion. In this case, the substantially planar continuous surface may be formed by the upper faces of the electrodes, the gate and the dielectric passivation layer, or by the upper faces of the electrodes and the metal portion. Slight variations in height or thickness may be due to the implementation of a chemical mechanical planarization (CMP) implemented in the presence of the electrode materials, the gate and the dielectric passivation layer, the speeds etching conductive materials of the electrodes (and possibly the gate when the latter is exposed at the upper face of the device) being different from that of the dielectric material of the passivation layer. These slight variations in height or thickness, between the upper faces of the dielectric passivation layer and those of the electrodes, may have the advantage of guaranteeing excellent insulation between the electrodes of the device and / or with respect to the gate and / or adjacent diode electrodes or grids when depressions are located at the upper faces of the electrodes and / or the gate. The optoelectronic device may comprise: several mesa structures; a plurality of dielectric passivation layers each covering at least a portion of the lateral flanks of at least a portion of the first and / or second semiconductor portion located at the level of the pn junction of one of the mesa structures and several electrically conductive grids such that each dielectric passivation layer is disposed between one of the grids and said at least a portion of the first and / or second semiconductor portion of one of the mesa structures, or several metal portions each covering at least a portion of the lateral flanks of at least a portion of the first and / or second semiconductor portion located at the pn junction of one of the mesa structures, and the second electrode can be electrically connected to the second semiconductor portion of each of the mesa structures, and the Higher aces of at least the first electrode of each of the mesa structures and the second electrode may form the substantially planar continuous surface. In this case: each of the mesa structures may be laterally surrounded at least in part by a first part of one of the dielectric passivation layers; each of the grids may laterally cover the first part of one of the dielectric passivation layers; a second part of each of the dielectric passivation layers can laterally cover one of the grids (which is therefore arranged between the first and the second part of one of the dielectric passivation layers), and the second electrode can cover laterally the second parts of the dielectric passivation layers, or else: each of the mesa structures may be laterally surrounded at least in part by one of the metal portions, and the second electrode may laterally cover the metal portions.
[0008] Alternatively: the grid may comprise at least a portion of at least one electrically conductive material extending in the mesa structure, or the metal portion may extend in the mesa structure, and the second electrode may be arranged around of the mesa structure. The optoelectronic device may comprise several mesa structures, and: the gate may comprise several portions of at least one electrically conductive material extending in one or more of the mesa structures, or several metal portions may extend in one or more of the mesa structures, and - the second electrode may be arranged around the or each mesa structures.
[0009] The optoelectronic device may further comprise an electrical contact disposed next to the mesa structure (s) and the second electrode, and to which the at least one grid or the metal portion or portions are electrically connected. The substantially planar continuous surface may be further formed by upper faces of the at least one grid or metal portion or portions, and / or upper faces of the at least one dielectric passivation layer, and / or the or each Dielectric passivation layers may cover an upper face of the or each of the grids. The optoelectronic device may further comprise at least one buffer layer comprising a semiconductor doped according to the same type of conductivity as the second semiconductor portion and on which the second semiconductor portion and the second electrode electrode are disposed. one next to the other. The optoelectronic device may further comprise a second doped semiconductor layer having a structured upper face, a first protruding portion forming the second semiconductor portion, and the second electrode may be disposed on at least a second portion of the second semiconductor layer. doped semiconductor forming a hollow of the structured face of the second doped semiconductor layer.
[0010] Alternatively, a first portion of the second semiconductor portion disposed between a second portion of the second semiconductor portion and the first semiconductor portion may form a setback relative to the second portion of the second portion of the semiconductor portion. semiconductor, and the second electrode can be electrically connected to the second semiconductor portion at an upper face of the second portion of the second semiconductor portion. The first semiconductor portion may be p-doped and may include at least one semiconductor having an acceptor activation energy of greater than or equal to about 200 meV, or the first semiconductor portion may be n-doped and may comprise at least one semiconductor having a donor activation energy of greater than or equal to about 200 meV. The invention also relates to an electronic device comprising one or more optoelectronic devices as described above and corresponding to one or more electroluminescent diodes and / or one or more photodiodes. The invention also relates to a method of light emission from an optoelectronic device as described above, comprising the implementation of a polarization of the optoelectronic device by the application of an electrical voltage between the one or more first electrodes and the second electrode of the optoelectronic device, and: the application of a difference of electrical potentials between the at least one metal grid or portions and the electrically connected electrode or electrodes to the doped semiconductor portion or portions; the electric potential applied to the at least one metal grid or portions is less than or equal to the electrical potential applied to the electrically connected electrode or electrodes to the p-doped semiconductor portion or portions, or electrical potentials between the one or more grids or metal portions and the electrodes or electrically connected to the or n-doped semiconductor portions such that the electrical potential applied to the at least one metal grid or portions is greater than or equal to the electrical potential applied to the at least one electrode electrically connected to the at least one doped semiconductor portion.
[0011] The invention also relates to a method of photoelectric conversion from an optoelectronic device as described above, comprising: the application of a difference of electrical potentials between the grid or metal portions and the electrode or electrodes electrically connected to the p-doped semiconductor portion (s) such that the electric potential applied to the at least one metal grid or portions is less than or equal to the electrical potential applied to the electrically connected electrode (s) connected to the semiconductor portion (s). p-doped conductor, or - the application of a difference in electrical potentials between the one or more grids or metal portions and the electrodes or electrodes electrically connected to the n-doped semiconductor portion or portions such that the electric potential applied to the or the grids or metal portions is greater than or equal to the electrical potential applied to the or electrodes electrically connected to the n-doped semiconductor portion (s). The invention also relates to a method for producing an optoelectronic device comprising at least the steps of: - producing a stack of layers comprising at least a first semiconductor layer arranged between a second semiconductor layer and a electrically conductive layer, one of the first and second semiconductor layers being p-doped and the other of the first and second semiconductor layers being doped n, etching of the multilayer stack , realizing at least one mena structure comprising a first and a second semiconductor portion forming a pn junction and a first electrode electrically connected to the first semiconductor portion, - producing an element capable of ionizing dopants of the pn junction via a generation of an electric field in the pn junction and covering at least a portion of the lateral flanks of at least a portion of the and / or the second semiconductor portion located at the pn junction, - producing a second electrode electrically connected to the second semiconductor portion, and wherein at least the realization of the second electrode comprises a planarization step of an electrically conductive material such that upper faces of at least the first electrode and the second electrode form a substantially flat continuous surface. Such a method has the advantage, in addition to those obtained by virtue of the presence of the element capable of ionizing dopants of the p-n junction, of requiring a limited number of steps for its implementation. There is also described a method of producing an electronic device, comprising the implementation of a method for producing at least one optoelectronic device as described above.
[0012] BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be better understood on reading the description of exemplary embodiments given purely by way of indication and in no way limiting, with reference to the appended drawings in which: FIG. 1 schematically represents an optoelectronic device, object of the present invention, according to a first embodiment; FIG. 2 diagrammatically represents the phenomenon of band curvature occurring in a light-emitting diode according to the invention; FIGS. 3 to 9 represent the internal quantum efficiency obtained as a function of the current density in different light-emitting diodes, objects of the present invention, for different values of a potential difference between the gate and the anode of these diodes electroluminescent; - Figures 10 and 11 show schematically an optoelectronic device object of the present invention, according to a second embodiment; FIG. 12 diagrammatically represents an optoelectronic device, object of the present invention, according to a variant of the second embodiment; FIGS. 13 and 14 diagrammatically show an optoelectronic device, object of the present invention, according to a third embodiment; - Figure 15 schematically shows an optoelectronic device object of the present invention, according to a variant of the third embodiment; FIGS. 16A to 16L schematically represent steps of a method for producing an optoelectronic device, object of the present invention, according to the second embodiment; FIGS. 17A to 17F schematically represent steps of a method for producing an optoelectronic device, object of the present invention, according to the third embodiment; FIG. 18 diagrammatically represents an optoelectronic device, object of the present invention, according to an alternative embodiment; FIG. 19 diagrammatically represents an electronic device, object of the present invention, comprising several optoelectronic devices, also objects of the present invention. Identical, similar or equivalent parts of the different figures described below bear the same numerical references so as to facilitate the passage from one figure to another.
[0013] The different parts shown in the figures are not necessarily in a uniform scale, to make the figures more readable. The different possibilities (variants and embodiments) must be understood as not being exclusive of each other and can be combined with one another. DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS FIG. 1 diagrammatically represents an optoelectronic device 100 according to a first embodiment. In this first embodiment, the optoelectronic device 100 corresponds to a light emitting diode, or LED. The LED 100 comprises a substrate 102, for example based on sapphire, intended to serve as a support for the growth of the other layers of the LED 100.
[0014] The LED 100 comprises an active zone 104 comprising one or more emitting layers each forming a quantum well, comprising for example InGaN, and being each disposed between two barrier layers, comprising for example GaN. InGaN comprises for example 16% of indium. All the layers of the active zone 104, that is to say the emitting layers and the barrier layers, comprise intrinsic semiconductor materials, that is to say unintentionally doped (concentration of residual donors) nn, d for example equal to about 1017 donors / cm3, or between about 1015 and 1018 donors / cm3). The thickness of the or each of the emitting layers is for example equal to approximately 2 nm and more generally between approximately 0.5 nm and 10 nm, and the thickness of each of the barrier layers is for example equal to approximately 5 nm. or between about 1 nm and 25 nm.
[0015] The active zone 104 is disposed between a first p-doped semiconductor portion 106 and a second n-doped semiconductor portion 108, the two semiconductor portions 106 and 108 forming the pn junction of the LED 100. (or more precisely the pin junction considering the active zone 104). The semiconductor portions 106 and 108 comprise for example GaN. The first portion 106 is p-doped with a concentration of acceptors (holes) for example between about 1017 and 5.1019 acceptors / cm3, and here equal to 1017 acceptors / cm3. The second portion 108 is n-doped with a concentration of donors (electrons) for example between about 1017 and 5.1019 donors / cm3, and here equal to 1017 donors / cm3. The two semiconductor portions 108 and 106, for example, each have a thickness of between approximately 20 nm and 10 μm. In the example described here, the first semiconductor portion 106 has a thickness equal to about 500 nm, and the second semiconductor portion 108 has a thickness of about 100 nm. The second semi-conductor portion 108 is disposed on a buffer layer 110, comprising, for example, n-doped GaN with a concentration of, for example, approximately 1019 donors / cm3 and a thickness of approximately 2 μm. The buffer layer 110 generally comprises the same semiconductor and is doped of the same type as the second portion 108. Semiconductor materials other than GaN and InGaN may be used to produce the LED 100, in particular according to the range of wavelengths to be emitted by the LED 100. The LED 100 also comprises a first portion of electrically conductive material, here metallic, disposed on the first semiconductor portion 106 and electrically connected thereto, thus forming a first electrode 112, here an anode, of the LED 100. The LED 100 is made by implementing an etching of a stack of the different layers used to form the elements of the LED 100 described above. In this first embodiment, however, the second semiconductor layer 111 forming the second semiconductor portion 108 is not etched throughout its thickness in order to keep portions 114 of this second semiconductor layer 111 adjacent to each other. to the second semiconductor portion 108 so that these n-doped semiconductor portions 114 are electrically connected to a second electrode 116 of the LED 100, which corresponds here to the cathode because the second portion 108 is n-doped. The second electrode 116 comprises for example a titanium layer of thickness equal to about 20 nm covered by an aluminum layer.
[0016] The second semiconductor layer 111 forming the second semiconductor portion 108 and the portions 114 may be seen as having a structured upper face, a first protruding portion forming the second semiconductor portion 108, the second electrode 116 being disposed on the second portions 114 of the second semiconductor layer 111 forming depressions of the structured face of this layer. Alternatively, the second semiconductor portion 108 and the portions 114 may be made from two separate layers of semiconductor superimposed one above the other. In this case, the semiconductor layer serving to form the second portion 108 is etched throughout its thickness, and that forming the parts 114 is not engraved (or can be partially engraved). The first electrode 112, the first semiconductor portion 106, the active zone 104 and the second semiconductor portion 108 of the LED 100 form a mesa structure 124, that is to say a stack in the form of an island, disposed on the substrate 104 (and on the buffer layer 110). The mesa structure 124 of the LED 100 has a section, in a plane parallel to the face of the substrate 102 on which this structure rests (plane parallel to the (X, Y) plane shown in FIG. 1), in the form of a disc or rectangular shape or any other shape, polygonal or not. The mesa structure 124 can therefore form an island, or pad, of cylindrical, parallelepipedal, and so on. The mesa structure 124 may also have an elongate shape, rectilinear or not, or any other form suitable for producing a light emitting diode. The mesa structure 124 of the LED 100 is surrounded by an electrically conductive grid 118. The gate 118 is formed of one or more electrically conductive materials, for example one or more metals such as aluminum. The thickness of the gate 118 (dimension along the X axis shown in FIG. 1, that is to say the dimension perpendicular to the lateral flanks of the mesa structure 124) is for example equal to approximately 100 nm, or included between about 3 nm and 10 μm. This gate 118 is electrically isolated from the pin junction of LED 100 (i.e. elements 104, 106 and 108) as well as electrodes 112 and 116 and n-doped semiconductor portions 114 by a layer. dielectric passivation 120 having for example SiN and a thickness equal to about 10 nm. The gate 118 surrounding the mesa structure 124 of the LED 100 is itself surrounded by the second electrode 116. A first portion of the dielectric passivation layer 120 is disposed between the lateral flanks of the mesa structure 124 and the gate 118. and a second portion of the dielectric passivation layer 120 is disposed between the gate 118 and the second electrode 116. Except for the upper face of the gate 118, the other faces of the gate 118 are in contact with the dielectric passivation layer 120. Given the mesa structure 124 of the LED 100 and the geometry of the second electrode 116, the gate 118 and the dielectric passivation layer 120, the upper faces (located at the top of the LED 100) of the first electrode 112 , the dielectric passivation layer 120, the gate 118 and the second electrode 116 together form a surface 122 substantially flat, that is to say, are arranged sensibl in the same plane. Given a step of planarization of the electrically conductive material of the second electrode 116 implemented during the realization of the LED 100 (step described below in connection with the production method), the upper faces of the first electrode 112, of the gate 118 and the second electrode 116 may optionally have depth cavities (with respect to the upper faces of the dielectric passivation layer 120) between 0 (no cavities) and about 150 nm. This substantially flat surface 122 is well adapted to be hybridized directly to another element, for example an electronic circuit comprising electrical contacts intended to be secured, for example by direct metal-metal bonding, to the anode and the cathode of the LED 100, and dielectric zones intended to be joined, also by direct dielectric-dielectric bonding, in particular to the dielectric passivation layer 120. The operating principle of such an LED 100 which, compared to a conventional LED, differs in particular because of the presence of the gate 118 around the mena structure 124, is described below.
[0017] The gate 118 arranged around the junction of the LED 100 makes it possible to create a field effect controlling the ionization of the dopants in the junction. Indeed, the electric field generated by the gate 118 disposed around the junction of the LED 100 makes it possible to ionize the acceptors of the first semiconductor portion 106 which is p-doped and to increase the recombination efficiency by injecting more of holes in the active area 104. The gate 118 is disposed around at least a portion of the first semiconductor portion 106 which is located near the junction of the LED 100, i.e. minus the portion of the first portion 106 in contact with the active zone 104 in the example of FIG. 1, so as to ionize the field effect acceptors on the surface of the gate at least at that portion of the first portion 106. To create the electric field, a potential difference is applied between the first electrode 112, forming the anode of the LED 100, and the gate 118 of the LED 100, which generates an electric field. In the case of a field effect transistor, the electric field generated by the gate makes it possible to invert the conductivity type of a zone and to create a conduction channel. Here, the electric field does not reverse the conductivity of the first p-doped semiconductor portion 106, but enhances its conductivity. Indeed, the quantity of ionized acceptors is fixed by the position of the level of the acceptors compared to the level of Fermi. Changing the curved surface potential strips the material of the second portion 106. The level of the acceptors is fixed with respect to the valence band. In particular, if the surface potential is reduced by applying on the gate 118 an electric potential lower than that applied on the anode 112, this curves the bands towards the negative energies so that close to the surface, the level of the acceptors in the first portion of p-doped semiconductor material 106 may pass (but not necessarily) below the fermi level. Near the surface, all the acceptors are then ionized. This curvature of the valence bands VB, conduction band CB, and the energy of the acceptors Ea with respect to the Fermi level Ef is shown diagrammatically in FIG. 2 at the interface between the first p-doped semiconductor portion. 106 and the dielectric passivation layer 120 when the electric potential applied to the gate 118 is lower than that applied to the anode 112.
[0018] The greater the difference between the potentials applied on the gate 118 and on the anode 112, the more the acceptors are ionized in depth. The ionized acceptors release holes that can recombine in the active zone 104 with the electrons from the second n-doped semiconductor portion 108 and create photons. Surface ionization of the field effect acceptors therefore increases the internal quantum efficiency of the LED 100 because more holes are available to recombine with the electrons from the n-doped semiconductor region. The diameter of the mesa structure 124, or the dimension of the sides of the mesa structure 124 perpendicular to the gate 118, is preferably less than or equal to about 50 μm when the mesa structure 124 comprises GaN, since the zone of The influence of the gate 118, i.e. the distance up to which the gate 118 can ionize acceptors in the p-doped semiconductor of the first portion 106, is of this order. When AIGaN is used, for example in the case of an active zone 104 in GaN or in AIGaN with quantum wells in AIGaN (with in this case an aluminum concentration lower than that in the barrier layers) or in GaN , requiring in this case greater ionization energies of the acceptors and therefore a need for a stronger electric field, the diameter, or the dimension of the sides surrounded by the gate 118, of the mesa structure 124 of the LED 100 is preferably less than or equal to about 5 microns. In any case, it is advantageous for the diameter, or the dimension of the sides surrounded by the grid 118, of the mesa structure 124 of the LED 100, to be less than or equal to approximately 5 μm. Simulations of the internal quantum efficiency of LED 100 made with Atlas Silvaco software are described below. FIG. 3 represents the internal quantum efficiency obtained in an LED of mesa structure and comprising a gate surrounding the p-doped semiconductor portion, as a function of the current density, in A / cm ', in the LED for different values. a potential difference Vg applied between the gate and the anode (Vg = Vgrille - Vanode). The LED used for this simulation has several structural differences with respect to the LED 100 described in connection with FIG. 1: the simulated LED does not include the parts 114 and the cathode 116 is not arranged around the gate 118 but is disposed under the second n-doped semiconductor portion 108, directly in contact therewith; the active zone 104 of the simulated LED is formed of a single InGaN quantum well comprising 16% indium and produced in a GaN layer that is not intentionally doped (results similar to those described below, however, would be obtained if the active zone 104 was formed by different elements); the p-doped semiconductor portions 106 and 108, the active zone 104 and the electrodes 112 and 116 are in the form of a cylindrical mena structure with a diameter of 1 μm; the gate 118 is not formed over the entire height of the junction of the LED but is formed only around the p-doped semiconductor portion 106, and is separated from this p-doped semiconductor portion 106 by a layer of dielectric passivation 120 in SiO 2 with a thickness of 5 nm. Curve 10 represents the internal quantum efficiency obtained in such an LED when Vg = OV. Curve 12 represents the internal quantum efficiency obtained in such an LED when Vg = -10V. By way of comparison, the curve represents the internal quantum efficiency obtained in a similar LED but having no grid formed around the junction of the LED. In addition, the curve 16 represents the internal quantum efficiency obtained in such an LED when Vg = 10V. By applying a voltage Vg = -10V, the internal quantum efficiency in the active zone 104 is greatly enhanced: it goes from about 20% when Vg = OV to more than 80% at most. On the other hand, when a positive Vg voltage is applied, the internal quantum efficiency becomes almost zero due to a particular curvature of the bands at the interface making the ionization of the acceptors even more difficult. These curves clearly illustrate the increase in the internal quantum efficiency obtained by applying a negative voltage Vg between the gate 118 and the anode 112 of the LED 100. This increase in the internal quantum efficiency of the LED is also obtained when the electrical potential applied to the gate 118 is zero compared to a similar LED having no gate. This is because when a voltage is applied between the anode 112 and the cathode 116 of the LED, by maintaining the cathode at OV and applying a positive voltage to the anode 112 to circulate a current, there exists then a potential difference between the p-doped semiconductor of the junction and the gate 118. This creates a field effect favoring the ionization of the acceptors in the p-doped semiconductor. FIG. 4 represents the internal quantum efficiency obtained in a LED of structure MLA and comprising a gate 118 surrounding the p-doped semiconductor portion 106, as a function of the current density, in A / cm ', in the LED for different values of a potential difference between the gate 118 and the anode 112. Compared with the LED used for the previous simulation whose internal quantum efficiency obtained is shown in FIG. 3, the LED used here comprises a gate 118 disposed around the entire junction, over the entire height of the junction, that is to say around the portions of doped semiconductors n 108 and p 106, and the active zone 104.
[0019] Curve 20 represents the internal quantum efficiency obtained in such an LED when Vg = OV. Curve 22 represents the internal quantum efficiency obtained in such an LED when Vg = -10V. Curve 24 represents the internal quantum efficiency obtained in a similar LED but having a gate formed around the junction of the LED. Curve 26 represents the internal quantum efficiency obtained in such an LED when Vg = 10V. As before, the internal quantum efficiency is greatly exalted when a negative or zero voltage Vg is applied, that is to say when the potential difference between the gate and the anode is zero or negative. We also see in this figure that for an LED whose gate 25 surrounds the junction over the entire height of the junction, for low current densities, for example less than about 250 A / cm ', it is even more interesting to work with a voltage Vg zero. This is due to the fact that in this geometry, the gate also has an effect on the ionization of the donors in the n-doped semiconductor of the LED. For a zero gate voltage, the field effect is low on the n side and hardly limits the ionization of the donors. On the other hand, because of the potential difference between the anode and the cathode (approximately 3.5 V), an already substantial field effect exists on the side p. The potential difference between the p-doped semiconductor and the gate makes it possible to ionize the surface acceptors of the p-doped semiconductor. For higher current densities, for example greater than about 400 A / cm 2, which limits the internal quantum efficiency in the case where a Vg voltage of OV is applied is the limited amount of ionized acceptors. In this case, it is preferable to use a negative voltage Vg, for example equal to about -10 V. FIGS. 5 and 6 show the internal quantum efficiency obtained in a mesa structure LED and comprising a grid surrounding the semi portion. p-doped driver, as a function of the current density, in A / cm ', in the LED for different potential difference values between the gate and the anode. With respect to the LED used for the previous simulation, the internal quantum efficiency obtained is shown in FIG. 4, the diameter of the mesa structure of the LED whose internal quantum efficiency is represented in FIG. 5 is equal to 5 μm. , and equal to 10 μm for Figure 6. The curves 30 and 40 represent the internal quantum efficiency obtained in these LEDs when Vg = OV. Curves 32 and 42 represent the internal quantum efficiency obtained in these LEDs when Vg = -10V. Curves 34 and 44 represent the internal quantum efficiency obtained in similar LEDs but having no grid formed around the junctions of the LEDs. Curves 36 and 46 represent the internal quantum efficiency obtained in these LEDs when Vg = 10V. Figures 4 to 6 illustrate that the effect of the electric field created by the grid is visible up to 10 μm menas diameters. In addition, this effect is notable up to mesa structure diameters of about 50 μm. FIGS. 5 and 6 also show that the effect remains interesting for lower current densities when the size of the mesa structure of the LED increases: in the case of a mesa structure of 5 μm in diameter, the quantum efficiency The internal drop drops to about 30% for a current density of 1000 A / cm 2 and a voltage V g of -10 V, whereas for a mesa structure of 10 μm in diameter, the internal quantum efficiency is about 20% for a current density of 1000 A / cm 2 and is about 40% for a current density of 300 A / cm 2. This field effect created by the grid deposited around a p-n or p-i-n junction is also very interesting in the case of p-n or pin junctions made from materials with larger gaps than that of GaN, such as AIGaN. In such materials, the ionization energy of acceptors is even higher than in GaN. Thus, in AlGaN, with about 40% aluminum, the ionization energy of the acceptors is about 300 meV. For AIN, the ionization energy of the acceptors is of the order of 600 meV. For AIN with about 70% aluminum, the ionization energy of the acceptors is of the order of 450 meV. The use of barrier layers with approximately 70% aluminum makes it possible to produce quantum wells with AlGaN with approximately 45% aluminum and to obtain light emission from these quantum wells at approximately 4.7 eV, ie at wavelengths of about 260 nm in the field of ultraviolet. This emission emission wavelength is very interesting because it is adapted to the disinfection of water because this wavelength of 260 nm kills the bacteria in the water. Figures 7 to 9 show the internal quantum efficiency obtained in a LED mesa structure emitting at a wavelength of about 260 nm. As in the previous simulations, the simulated LED does not include the parts 114 and the cathode 116 is not arranged around the gate 118 but is disposed under the second n-doped semiconductor portion 108, directly in contact with it. The p-and n-doped semiconductor portions 106 and 108 comprise Al0.7Ga0.3N with a concentration equal to 1017 acceptors / cm3 for the p-doped portion 106 and a concentration equal to 1018 donors / cm3 for the n-doped portion 108. The active zone 104 of the simulated LED comprises a single Al0.4Gao, 6N quantum well made in a layer of Al0.7Go, 3N unintentionally doped and with a residual donor concentration nn, d equal to about 1017 donors. cm3, forming the barrier layers of the active zone 104. The p-and n-doped semiconductor portions 106 and 108, the active zone 104 and the electrodes 112 and 116 are formed in the form of a diameter cylindrical mena structure. equal to 1 μm for FIG. 7, at 5 μm for FIG. 8 and at 10 μm for FIG. 9. In addition, gate 118 is made over the entire height of the junction of the LED, around the doped semiconductor portions. p and n 106 and 108, and around the active area 104. The curves 50, 60 and 70 represent the internal quantum efficiency obtained in these LEDs when Vg = OV. The curves 52, 62 and 72 represent the internal quantum efficiency obtained in these LEDs when Vg = -10V. Curves 54, 64 and 74 represent the internal quantum efficiency obtained in similar LEDs but having no grid formed around the junction of the LED. The curves 56, 66 and 76 represent the internal quantum efficiency obtained in these LEDs when Vg = 10V. As before, the curves shown in FIGS. 7 to 9 show that the internal quantum efficiency of such an LED can be greatly increased by using a gate 118 around the junction. This would also be the case as long as the gate 118 is arranged facing at least a portion of the p-doped semiconductor portion 106, at the interface with the active zone 104.
[0020] The gate 118 also makes it possible to compensate for the deleterious effects of a possible too strong doping n, d in the active zone 104 or a possible too weak doping of the p-doped semiconductor portion 106. The effect of the gate around the p-doped semiconductor is beneficial regardless of the structure of the active zone: with or without an electron blocking layer, and regardless of the number of quantum wells. In the case of an LED having a p-type AIGaN electron blocking layer disposed between the p-doped semiconductor portion 106 and the active area 104, it is also beneficial to form the gate 118 around the layer. electron blocking. The presence of this grid also makes it possible to have good internal quantum efficiencies without using an electron blocking layer in the LED. In the embodiment previously described in connection with FIG. 1, the gate 118 is made around the first electrode 112, the first portion of p-doped semiconductor material 106, the active zone 104, and a portion of the height (dimension along the Z axis) the second portion of n-doped semiconductor material 108. As a variant, the gate 118 can be made over the entire height of the junction of the LED 100, that is, also in the whole height of the second portion of n-doped semiconductor material 108. According to other variants, the gate 118 can be made: - only around the first electrode 112, the first semiconductor portion p-doped conductor 106 and active area 104, or - only around the first electrode 112, the first p-doped semiconductor portion 106 and a portion of the active area 104, or else - only around the first electrode 112 and of the first p-doped semiconductor portion 106, or - only around the first p-doped semiconductor portion 106 (with in this case a material bridging the space between the top of the gate 118 and the upper face 122 which is substantially planar), or - only around a portion of the first p-doped semiconductor portion 106 which is located at the junction, i.e. in contact with the active zone 104 (with in this case a material filling the space between the top of the gate 118 and the upper face 122 which is substantially flat). In addition, it is possible that the gate 118 only partially surrounds the elements of the mesa structure 124 mentioned above. The gate 118 may be arranged at one or more sides of the mesa structure 124 of the LED 100.
[0021] An electron-blocking layer, for example made of AlGaN with an aluminum concentration between 8% and 15% and p-doped, can also be placed between the active zone 104 and the first p-doped semiconductor portion 106. Alternatively, the mesa structure 124 of the LED 100 may not have the active area 104, and the first p-doped semiconductor portion 106 is then disposed directly on the second n-doped semiconductor portion 108. The mesa structure 124 of the LED 100 can form a pad of a section of any shape, or a portion of elongate shape (rectilinear or curved), or even a portion of any other form as long as this form of the mesa structure 124 allows to form a light emitting diode. As a variant of the SiN used to produce the dielectric passivation layer 120, this dielectric passivation layer 120 may comprise a High-k type dielectric material such as HfO 2 or ZrO 2, which makes it possible to obtain in the mesa structure 124 a electric field greater than in the case of a dielectric passivation layer 120 formed with a dielectric material of lower electrical permittivity such as SiN.
[0022] The SiN dielectric passivation layer 120 may advantageously have a thickness of at least 50 nm to prevent breakdown when the potential difference between the gate and the anode can reach about 15 V. Preferably, the thickness of the layer dielectric passivation 120 is chosen such that it can withstand a potential difference of about 20 V without breakdown, this thickness being a function of the material used to make the dielectric passivation layer 120. Several LEDs similar to the LED 100 can be realized next to each other on the substrate 102. In addition, the second layer of n-doped semiconductor can form a base common to all the LEDs and form all the second portions 108 of these LEDs. The second electrodes 116 of these LEDs can form in this case a common electrode, for example a common cathode, to all the LEDs, the individual addressing of the LEDs being carried out via the first electrode 112 specific to each of the LEDs. Although it is preferable to set the electrical potential of the grid of each of the LEDs to control the ionizing effect of the dopants, it is possible that this potential is not fixed and is left floating, and that only the potentials applied on the electrodes are fixed.
[0023] FIGS. 10 and 11 respectively represent a sectional view (along axis AA 'shown in FIG. 11) and a schematic top view of an optoelectronic device 100 according to a second embodiment, here an LED, comprising several regions. forming mesa structures 124a, 124b and 124c arranged next to each other. The mesa structures 124a, 124b and 124c of the LED 100 according to this second embodiment are formed of the same layers of materials as those forming the mesa structure 124 of the LED 100 according to the first embodiment. The mesa structures 124a, 124b and 124c of the LED 100 form schematically several slender portions (three on the embodiment shown in FIGS. 10 and 11) arranged parallel to one another, and each surrounded by a grid 118. In addition, the profile of each of these portions is here not completely rectilinear and has "recesses" 126 for increasing the contact surface of the grids 118 with mesa structures 124a, 124b and 124c. Furthermore, in this second embodiment, the upper surfaces of the grids 118 which form a part of the upper planar surface 122 in the first embodiment are here covered by electrical contacts 119 themselves covered by parts of the layers of Dielectric passivation 120 which completely surrounds the gates 118 and the electrical contacts 119. The gates 118 are electrically accessible via an electrical contact 128 remote or remote relative to the other elements of the LED 100 and to which are connected the gates 118 of the LED 100 via the electrical contacts 119. As in the first embodiment, the second n-doped semiconductor layer 111 forms the n-doped portions 108 and the portions 114 on which the second electrodes 116 forming the cathodes reside. . The second electrodes 116 are electrically connected to the second n-doped portions 108 via the portions 114 of this second n-doped semiconductor layer 111. In addition, the LED 100 according to the second embodiment has the upper surface 122 which is substantially flat. and formed by the upper faces of the electrodes 112 and 116 as well as the upper faces of the dielectric passivation layers 120 (which cover the grids 118 and the electrical contacts 119). The electrodes 112 and 116 may for example be formed by the superposition of several electrically conductive materials. The mesa structures 124a, 124b and 124c could be of a completely different shape than those represented in the example of FIGS. 10 and 11. In addition, the various variants and details of embodiment previously described for the first embodiment (relative to materials used, to the elements of the mesa structure surrounded by the grid, to the grid surrounding or not completely the mesa structure, etc.) can also be applied to the second embodiment. FIG. 12 represents a profile sectional view of an optoelectronic device 100 according to a variant of the second embodiment previously described. In this variant, a first portion 123 of the second semiconductor portion 108 disposed between a second portion 125 of the second semiconductor portion 108 and the active zone 104 forms a recess, or a recess, relative to the second portion 125 of the second semiconductor portion 108. A first portion of each of the second electrodes 116 traverses the entire second n-doped semiconductor layer 111 as well as the buffer layer 110 and rests directly on the substrate 102. A second part of each second electrodes 116 adjacent to the first portion rests on an upper face 127 of the second portion 125 of the second semiconductor portion 108, and is electrically connected to the second portion 108 of the adjacent mesa structure at this upper face. 127. Each of the mesa structures 124a, 124b and 124c is surrounded by the grid 118 which extends on one side (which does not comprise the recess) over the entire height of the mesa structure and the other (which includes the recess) on only part of the height of the mesa structure. The portion of the grid 118 which is located at the recess rests on the upper face 127. Part of the dielectric passivation layer 120 is interposed between the gate 118 and the upper face 127. This variant has the advantage of allowing interconnection in series optoelectronic devices by connecting, for each interconnected device, the second electrode 116 to the first electrode 112 of the adjacent device.
[0024] This variant of the second embodiment can also be applied to the first embodiment previously described. FIGS. 13 and 14 respectively represent a sectional view (along axis AA 'shown in FIG. 14) and a schematic top view of an optoelectronic device 100, here an LED, according to a third embodiment LED 100 comprises a single mesa structure 124 which, in the example of Figures 13 and 14, comprises a section, in the plane (X, Y), of substantially rectangular shape, and is formed of the same layers of materials as those forming the mesa structure. 124 of the LED 100 according to the first embodiment. In this third embodiment, the mesa structure 124 is not surrounded by the gate 118 but is traversed by several portions of electrically conductive material 118a-118e (5 in the example of Figures 13 and 14) s' extending into the mesa structure 124 and forming the gate 118 together. In the example described here, the portions 118a-118e correspond to rectilinear portions extending in a direction parallel to the substantially planar surface 122 (parallel to the Y axis in Figure 14). Each of the portions of electrically conductive material 118a-118e is surrounded, at the level of the lateral flanks and the lower face of these portions, of the dielectric passivation layer 120 ensuring the electrical insulation between the portions 118a-118e and the materials of the Mesa structure 124. In this third embodiment, the dielectric passivation layer 120 advantageously comprises a High-k type dielectric material such as HfO 2 or ZrO 2, but could also comprise a dielectric material of lower permittivity. The portions of electrically conductive material 118a-118e are electrically connected to the electrical contact 128 offset from the other elements of the LED 100.
[0025] The second electrode 116 is formed by a portion of electrically conductive material surrounding the mesa structure 124, as in the first embodiment, and in contact with the buffer layer 110 which provides the electrical connection between the second electrode 116 and the second portion of N-doped semiconductor portion 108. Portions of the dielectric passivation layer 120 also cover the outer lateral flanks of the mesa structure 124 and thereby electrically isolate the other elements of the mesa structure 124 (first electrode 112, first p-doped semiconductor portion). 106, active zone 104) vis-à-vis the second electrode 116.
[0026] With such a structure, the internal quantum efficiency of the LED 100 is improved thanks to the presence of the gate 118 in the mesa structure 124 which makes it possible to generate an electric field in a manner analogous to the previous embodiments in which the grid or grids 118 surround the mesa structure (s). The portions of electrically conductive material 118a-118e forming the gate 118 may have a different shape, rectilinear or not, from that of the example of FIGS. 13 and 14, and / or the gate 118 may comprise a different number of portions of material. electrically conductive forming the gate 118, in particular according to the dimensions of the mesa structure 124 of the LED 100.
[0027] The characteristics previously described for the first embodiment relating to the diameter of the mesa structure as a function of the materials used apply in a similar manner to the distances between the portions of electrically conductive material 118a-118e forming the grid 118, depending on the materials forming the mesa structure 124 of this LED 100.
[0028] The different variants and details of embodiment previously described for the two previous embodiments can also be applied to this third embodiment. FIG. 15 represents a view from above of an optoelectronic device 100 according to a variant of the third embodiment.
[0029] According to this variant, the mesa structure 124 is formed of several studs, or islands, arranged next to each other, of cylindrical, parallelepipedal or other shape. In the example of Figure 15, nine pads 124a - 124i are arranged forming a 3x3 matrix. The gate 118 is formed by portions of electrically conductive material 118a-118f (six in the example of Figure 15) extending through the pads 124a-124i. Each of the pads 124a 124i is crossed by two of the portions 118a-118f in the example of Figure 15, but could alternatively be traversed by a different number of portions of electrically conductive material forming the grid 118. Each of the pads 124a - 124i is surrounded by a portion of the dielectric passivation layer 120 for electrically isolating the second electrode 116 which surrounds each of the pads 124a - 124i. The number and / or the shape of the pads forming the mesa structure 124, as well as the number and / or the shape of the portions of electrically conductive material forming the gate 118 may be different from those of the example of FIG. the embodiments, the gate 118 is advantageously made as "dense" as possible with respect to the mesa structure or structures 124, that is to say such as the contact surface between the gate 118 and the mesa structure (s). 124 be the largest possible. FIGS. 16A to 16L schematically represent the steps of a method for producing the optoelectronic device 100, here an LED, according to the second embodiment. These figures represent cross sectional views of the structure forming the optoelectronic device 100.
[0030] As shown in FIG. 16A, the stack of layers from which the mesa structures 124 of the LED 100 are to be made is first produced on the substrate 102. This stack comprises, in the direction from the upper face of the stack to the bottom face of the stack in contact with the substrate 102, a first p-doped semiconductor layer 115 (here comprising GaN), active layers 113 corresponding to an alternating stack of one or more quantum well emissive layers, comprising for example InGaN, and barrier layers, comprising for example GaN, a second n-doped semiconductor layer 111, for example comprising GaN, and the buffer layer 110, comprising, for example, n-doped GaN. The first electrodes 112 intended to form the anodes of the LED 100 are then produced on the first p-doped semiconductor layer 115, for example via a deposition and then a lithography and etching of a first layer of electrically conductive material, comprising for example aluminum. The first electrodes 112 each have a shape and dimensions, in the plane of the upper face of the first p-doped semiconductor layer 115 on which they are made, substantially similar to those desired for the mesa structures 124 of the LED 100 , and for example a disc-shaped section. A hard mask 131 is formed on the first layer of electrically conductive material intended to form the first electrodes 112 such that openings formed in this mask 131 correspond to the patterns to be etched in the stack of layers on which the hard mask 131 is formed so to define the first electrodes 112 and the mesa structures 124 of the LED 100. In the embodiment described here, the portions of the hard mask 131 have a shape and dimensions, in the plane of the upper face of the first layer of p-doped semiconductor 115 on which the first electrodes 112 are made, substantially similar to those of the first electrodes 112.
[0031] As shown in FIG. 16B, an etching of the first p-doped semiconductor layer 115, active layers 113 and a portion of the thickness of the second n-doped semiconductor layer 111 is also implemented. in the pattern defined by the hard mask 131, forming the mesa structures 124a, 124b and 124c, for example of cylindrical shape, each comprising the active zone 104 disposed between the first p-doped semiconductor portion 106 and the second portion of semi This etching is stopped at a level of depth located in the second n-doped semiconductor layer 111 such that a portion 114 of this second layer 111 is kept at the bottom of each of the etched areas of the n-doped semiconductor layer. stacking (on which the second electrodes 116 will rest). This etching step forms, around the mesa structures 124, empty spaces 133 which will subsequently be used for the production of the second electrodes 116, the dielectric passivation layer 120 and the grids 118. The etching implemented is a dry etching for example reactive ion etching with a C12 plasma. This etching delimits the mesa structures 124. The hard mask 131 can be deleted or not before the implementation of the following steps. In addition, the etching of the electrodes 112 and that of the mesa structures 124 are preferably implemented during the same etching step. A first dielectric layer 121, comprising, for example, SiN or a high-k dielectric material according to the desired material to form the dielectric passivation layer 120, is then deposited with a thickness that is consistent, for example equal to 10 nm, over the portions of the hard mask 131 and along the walls of the empty spaces 133, thus covering the side walls of the first electrodes 112, the first p-doped semiconductor portions 106, the active zones 104 and the second n-doped semiconductor portions 108. This first dielectric layer 121 is also deposited on the unetched portions 114 of the second n-doped semiconductor layer 111 forming the bottom walls of the void spaces 133. A second layer of electrically conductive material 134 intended to form the grids 118, for example aluminum and thickness equal to about 500 nm, is then deposited in a manner consistent on the first neck Dielectric layer 121. A second dielectric layer 136, for example comprising SiN or a high-k dielectric material and having a thickness equal to 100 nm, or more generally at least 5 nm, is then deposited on the second layer of material. electrically conductive 134 (Figure 16C). A directional etching of the second dielectric layer 136, via a SF6 plasma, and the second layer of electrically conductive material 134, via an argon-type plasma Cl2, is then implemented such that remaining portions of the second dielectric layer 136 and the second layer of electrically conductive material 134 cover the side walls of the voids 133, that is to say the lateral flanks of the mesa structures 124 (Figure 16D). The remaining portions of the second layer of electrically conductive material 134 form the grids 118 surrounding the mesa structures 124, and the remaining portions of the dielectric layers 121 and 136 form portions of the dielectric passivation layer 120. Advantageously, the dielectric layer 121 and the layer of electrically conductive material 134 are etched before the deposition of the second dielectric layer 136. The second dielectric layer 136 is then deposited, which makes it possible to surround the lower portions of the remaining portions of the conductive layer 134 with a dielectric as shown in FIG. 16D. Another etching may then be implemented to form the accesses to the second n-doped semiconductor layer 111 between the mesa structures 124. A deposition of a third layer of electrically conductive material 138 is then produced in order to fill the gaps voids 133 (Figure 16E). This deposit is made on the entire structure and also covers the mesa structures 124. This deposit is for example obtained via a deposit of a titanium layer of thickness equal to about 20 nm, and then a deposit of a layer aluminum thickness of about 1 iim. As shown in FIG. 16F, a chemical mechanical planarization (CMP) is then implemented in order to remove the parts of the third layer 138 covering the mesa structures 124 and also to remove the portions of the passivation layer 120 covering the mesa structures. 124. This CMP is implemented by taking as the stop surface the upper faces of the first electrodes 112. The remaining portions of the layer 138 form the second electrodes 116. A deposit of a third dielectric layer 140, comprising for example SiN or a high-k dielectric, and of thickness equal to about 100 nm, is then produced, this third dielectric layer 140 then being etched so that remaining portions of this third dielectric layer 140 do not cover the grids 118 (FIG. 16G ). A deposit of a fourth layer of electrically conductive material 142 is then made over the entire structure (FIG. 16H) in order to perform, after an etching, the electrical contacts 119 on the grids 118 as well as the remote electrical contact 128 with respect to the structures mesa 124 and to which the grids 118 are connected via the electrical contacts 119. This electrically conductive material corresponds for example to aluminum deposited to a thickness of about 100 nm. As shown in FIG. 161, a fourth dielectric layer 143 (SiN or high-k dielectric) is deposited on the fourth layer of electrically conductive material 142, then this fourth dielectric layer 143 and the fourth layer of electrically conductive material 142 are etched to that remaining portions of the fourth layer of electrically conductive material 142 form the electrical contacts 119 disposed on the grids 118 and electrically connect the grids 118 to the remote contact 128, and that remaining portions of the fourth dielectric layer 143, forming part of the dielectric passivation layer 120, cover the electrical contacts 119. Parts of the third dielectric layer 140 covering the electrodes 112 and 116 are also etched to form accesses to the electrodes 112 and 116.
[0032] A fifth layer of dielectric material 146 (SiN or High-k dielectric) is deposited over the entire structure, for example with a thickness equal to about 100 nm (FIG. 16J), then the portions of this fifth dielectric layer 146 covering the electrodes 112 and 116 are etched to form ports to the electrodes 112 and 116 (Fig. 16K). Remaining portions of this fifth layer of dielectric material 146 overlap the side flanks of the electrical contacts 119 and form, along with the remaining portions of the other dielectric layers, the dielectric passivation layers 120 surrounding the grids 118 and the electrical contacts 119.
[0033] The LED 100 is completed by depositing a fifth layer of electrically conductive material over the entire structure and implementing a CMP with stop on the dielectric passivation layers 120, thus forming metal portions extending the electrodes 112 and 116 to at the same level as the dielectric passivation layers 120 (FIG. 16L). This last stage of CMP can form, at the level of the substantially flat upper face 122, the slight cavities at the level of the metal contacts with respect to the dielectric passivation layers 120. FIGS. 17A to 17F represent the steps of a method for producing the optoelectronic device 100, here an LED, according to the third embodiment previously described. These figures represent cross-sectional views of the structure intended to form the LED 100. As shown in FIG. 17A, the stack of layers is first produced on the substrate 102 from which the structure LED 100 will be realized. This stack is similar to that previously described in connection with FIG. 16A. In addition, the first electrodes 112 and the hard mask 131 are made on the structure previously formed such that openings formed in this mask 131 correspond to the patterns to be etched in the layer stack on which the hard mask 131 is formed in order to define the locations in which the gate 118 will pass through the mesa structure 124 of the LED 100. As shown in FIG. 17B, etching of the first p-doped semiconductor layer 115, the active layers 113 and the second semiconductor layer. 111 doped conductor and a portion of the thickness of the buffer layer 110 is then implemented in the pattern defined by the hard mask 131, forming in the mesa structure 124 locations 148 in which the electrically conductive portions of the gate 118 are intended to cross the mesa structure 124. This etching is also performed on the periphery of the mesa structure 124 to form the locations 15 0 at which the second electrode 116 will be made. This etching is stopped at a depth level located in the buffer layer 110. It is possible, however, that this etching is stopped at another level, for example at the upper face of the buffer layer 110 or in the layer 111.
[0034] The etching used is a dry etching, for example a reactive ion etching with a plasma of Cl2. The dielectric passivation layer 120 is then deposited in a conformal manner on the structure, that is to say both on the mesa structure 124 and in the locations 148 and 150 covering all the walls (side walls and walls background) of these locations (Figure 17C). This dielectric passivation layer 120 is for example here Hf02 deposited by ALD. The portions of the dielectric passivation layer 120 covering the bottom walls of the locations 150 of the second electrode 116 are then etched, for example via a type C1 plasma etching, by masking the other parts of the dielectric passivation layer 120 to be preserved, for example with resin (Figure 17D). A deposit of a layer of electrically conductive material 152 full plate is then made, filling the locations 148 and 150 (Figure 17E), then a CMP is implemented with a stop on the first electrodes 112, thus forming the second electrode 116 and the dielectric passivation layer 120. In a variant of GaN, InGaN and AIGaN, the pn or pin junction of the optoelectronic device 100 can be made from ZnO. For the realization of such a junction, a two-dimensional ZnO heterostructure comprising quantum wells of ZnCdO or ZnMgO can be first performed. P type implantation and annealing of this heterostructure can then be carried out, as described for example in document FR 2 981 090 A1. A structure similar to that shown in FIG. 16A is then obtained, in which the layer 115 corresponds to a p-doped ZnO layer (obtained for example by phosphorus implantation), the active layers 113 correspond to ZnO / ZnCdO or ZnO / ZnMgO wells, and the 111 layer corresponds to an n-doped ZnO layer. Similar steps to those previously described in connection with FIGS. 16B to 16L can then be implemented from such a stack to complete the implementation of the device 100. In all the embodiments and variants described above, each element comprising a gate and the passivation layer arranged around the gate and which makes it possible to ionize the junction dopants via a generation of an electric field in the junction can be replaced by one or more metal portions forming one or more Schottky contacts with the materials of the pn or pin junction. In this case, the metal portion or portions are directly in contact with the semiconductor materials of the junction, without insulating material disposed between the semiconductor materials and the metallic material. To form such a Schottky contact, the metal used is selected from metals having a high output work, such as for example tungsten whose work output is equal to about 6.1 eV, or platinum. The choice of the metal used to form such Schottky contacts depends on the structure of the optoelectronic device 100, the semiconductor materials used, etc. FIG. 18 represents an exemplary embodiment of such an optoelectronic device 100, here of similar structure to the device 100 previously described in connection with FIGS. 13 and 14, but in which the led structure 124 is traversed by metal portions 154 forming Schottky contacts with semiconductor materials forming the pn junction. As a variant of the various embodiments previously described, it is possible for the junction of the optoelectronic device 100 to be made on a diamond basis, for example in the case of an LED or a photodiode capable of producing a transmission or detection of UV light. The stack of layers from which such a device can be made can be formed from a naturally p-type graphite substrate. A p-type diamond growth is then carried out, and then an n-type diamond layer is produced, for example as described in the document by S. Koizumi et al., "Growth and characterization of phosphorous doped {111} homoepitaxial diamond thin films », Appl. Phys. Lett. 71, 1065 (1997), that is to say by CVD growth using phosphine as dopant, over a thickness for example equal to about 300 nm. Steps analogous to those previously described in connection with FIGS. 16B to 16L can then be implemented from such a stack to complete the production of the device 100. With such a diamond-based optoelectronic device, the grid (s) or Schottky contacts are not used to ionize acceptors but to ionize donors in n-doped diamond that have high activation energy. Thus, the gate or the Schottky contact or contacts are made such that they cover at least a portion of the lateral flanks of at least a portion of the doped semiconductor portion n located at the junction p-n. or p-i-n, which will be positively polarized (positive Vg voltage) in order to increase the internal quantum efficiency in the junction. In this configuration, the first semiconductor portion 106 is advantageously made with an n-type semiconductor. One or more LEDs 100 according to one of the various embodiments previously described may be integrated within a light emitting device 1000. FIG. 19 schematically represents such a device 1000 comprising 9 LEDs 100 produced on the same substrate 102 under the form of a 3x3 matrix. In a variant of the various embodiments described above, reference 100 may correspond not to one or more LEDs, but to one or more photodiodes having p-n or p-i-n junctions. As for the LEDs, the grids or Schottky contacts are used in this case to ionize the dopants (acceptors or donors) and thus adjust the doping in the junction used to perform the photoelectric conversion. For example, for a photodiode 100 intended to carry out UV light detection, if AIGaN is used to make the pn junction (for example made by MOCVD growth of n-type AIGaN with approximately 50% of aluminum doped with silicon at 1019 donors / cm3 over a thickness of about 1 μm and then at 1017 donors / cm3 over a thickness of about 500 nm, then growth of p-type AIGaN doped with magnesium at about 1019 acceptors / cm3 over a thickness of approximately 300 nm) the problem related to the high activation energy of acceptors in the p-type semiconductor found in such a photodiode, limiting the performance for the detection of UV light. Similarly, the use of an n-type semiconductor having a high donor activation energy, for example diamond, is also possible for the production of a photodiode. In this case, the grids or Schottky contacts make it possible to ionize these donors in order to improve the conductivity of the n-type semiconductor. In addition, the device 1000 shown in FIG. 19 may correspond not to a light emitting device but to a photodetector device comprising several photodiodes 100. The ionization of the dopants carried out thanks to the gate (s) or contact (s) or contact ( s) Schottky responds to this problem in a similar way to that previously described for LEDs. In the case of an optoelectronic device 100 for performing a photoelectric conversion such as a photodiode, the electrode or electrodes 112 at the top of the structures mena are made from a material transparent to the wavelengths intended to be detected and converted photoelectrically, for example ITO with a thickness of about 100 nm. The second electrodes 116 serve in this case of electron collectors.

权利要求:
Claims (17)
[0001]
REVENDICATIONS1. Optoelectronic device (100) comprising at least one mena structure (124) comprising at least: a first (106) and a second (108) semiconductor portion, one being p-doped and the other being n-doped, and together forming a pn junction, - a first electrode (112) electrically connected to the first semiconductor portion (106) which is disposed between the second semiconductor portion (108) and the first electrode (112), the optoelectronic device (100) further comprising at least: - a second electrode (116) electrically connected to the second semiconductor portion (108), - an element (118, 120, 154) capable of ionizing dopants of the junction pn via a generation of an electric field in the pn junction and covering at least a portion of the lateral flanks of at least a portion of the first (106) and / or second (108) semiconductor portion located at the level of the pn junction, and in the leq uel of the upper faces of at least the first electrode (112) and the second electrode (116) form a substantially planar continuous surface (122).
[0002]
Optoelectronic device (100) according to claim 1, wherein the element capable of ionizing dopants pn junction comprises: - at least one dielectric passivation layer (120) covering said at least a portion of the side flanks of at least a portion of the first (106) and / or the second (108) semiconductor portion located at the pn junction and at least one electrically conductive grid (118) such as the dielectric passivation layer (120) is disposed between the gate (118) and said at least a portion of the first (106) and / or the second (108) semiconductor portion, and / or - at least one metal portion (154) covering said at least one at least a portion of the side flanks of at least a portion of the first (106) and / or the second (108) semiconductor portion located at the pn junction and forming a Schottky contact with said at least a portion of the first (106) and / or the the second (108) semiconductor portion.
[0003]
An optoelectronic device (100) according to claim 2, wherein: - a first portion of the dielectric passivation layer (120) laterally surrounds at least a portion of the first electrode (112), the first semiconductor portion (106); ) and at least a portion of the second semiconductor portion (108), - the gate (118) laterally covers the first portion of the dielectric passivation layer (120), - a second portion of the dielectric passivation layer ( 120) laterally covers the gate (118), and the second electrode (116) laterally covers the second portion of the dielectric passivation layer (120), or wherein: the metal portion (154) laterally surrounds in part the first electrode (112), the first semiconductor portion (106) and at least a portion of the second semiconductor portion (108), and - the second electrode (116) laterally covers the portion on metal (154).
[0004]
Optoelectronic device (100) according to one of claims 2 or 3, comprising: - several mesa structures (124), - several dielectric passivation layers (120) each covering at least a portion of the side flanks of at least one part of the first (106) and / or the second (108) semiconductor portion located at the pn junction of one of the mesa structures (124) and a plurality of electrically conductive grids (118) such as each dielectric passivation layer (120) is disposed between one of the grids (118) and said at least a portion of the first and / or second semiconductor portion of one of the mesa structures (124), or a plurality of metal portions (154). ) each covering at least a portion of the lateral flanks of at least a portion of the first (106) and / or the second (108) semiconductor portion located at the pn junction of one of the mesa structures (124) , in which the second el the electrode (116) is electrically connected to the second semiconductor portion (108) of each of the mesa structures (124), and wherein the upper faces of at least the first electrode (112) of each of the mesa structures (124) ) and the second electrode (116) form the substantially planar continuous surface (122).
[0005]
An optoelectronic device (100) according to claim 4, wherein: - each of the mesa structures (124) is laterally surrounded at least in part by a first portion of one of the dielectric passivation layers (120), - each of the grids (118) laterally covers the first portion of one of the dielectric passivation layers (120), - a second portion of each of the dielectric passivation layers (120) laterally covers one of the grids (118), and - the second electrode (116) laterally overlaps the second portions of the dielectric passivation layers (120), or wherein: - each of the mesa structures (124) is laterally surrounded at least in part by one of the metal portions (154), and - the second electrode (116) laterally covers the metal portions (154). 10
[0006]
Optoelectronic device (100) according to claim 2, wherein: the gate (118) comprises at least a portion of at least one electrically conductive material extending in the mesa structure (124), or the metal portion (154) extends into the mesa structure (124), and - the second electrode (116) is disposed around the mesa structure (124).
[0007]
An optoelectronic device (100) according to claim 2, having a plurality of mesa structures (124), and wherein: - the gate (118) has a plurality of portions of at least one electrically conductive material extending into one or more of mesa structures (124), or a plurality of metal portions (154) extend into one or more of the mesa structures (124), and the second electrode (116) is disposed around the or each of the mesa structures (124). .
[0008]
Optoelectronic device (100) according to one of the preceding claims, further comprising an electrical contact (128) disposed next to the one or more structures mena (124) and the second electrode (116), and to which the one or more grids (118) or the metal portion or portions (154) are electrically connected.
[0009]
The optoelectronic device (100) according to one of the preceding claims, wherein the substantially planar continuous surface (122) is further formed by upper faces of the at least one grid (118) or metal portion or portions (154). ), and / or by upper faces of the dielectric passivation layer or layers (120), and / or wherein the or each of the dielectric passivation layers (120) covers an upper face of the or each of the grids (118). ).
[0010]
Optoelectronic device (100) according to one of the preceding claims, further comprising at least one buffer layer (110) comprising a semiconductor doped according to the same type of conductivity as the second semiconductor portion (108) and on which are disposed the second semiconductor portion (108) and the second electrode (116) next to each other.
[0011]
An optoelectronic device (100) according to one of the preceding claims, further comprising a second doped semiconductor layer (111) having a structured top face, a first protruding portion of which forms the second semiconductor portion (108), and wherein the second electrode (116) is disposed on at least a second portion of the second doped semiconductor layer (111) forming a recess of the structured face of the second doped semiconductor layer (111).
[0012]
Optoelectronic device (100) according to one of claims 1 to 10, wherein a first portion (123) of the second semiconductor portion (108) disposed between a second portion (125) of the second portion of semi -conductor (108) and the first semiconductor portion (106) forms a recess with respect to the second portion (125) of the second semiconductor portion (108), and wherein the second electrode (116) is electrically connected to the second semiconductor portion (108) at an upper face (127) of the second portion (125) of the second semiconductor portion (108).
[0013]
Optoelectronic device (100) according to one of the preceding claims, wherein the first semiconductor portion (106) is p-doped and comprises at least one semiconductor whose acceptor activation energy is greater than or equal to at about 200 meV, or wherein the first semiconductor portion (106) is n-doped and includes at least one semiconductor having a donor activation energy of greater than or equal to about 200 meV.
[0014]
14. An electronic device (1000) comprising one or more optoelectronic devices (100) according to one of the preceding claims corresponding to one or more light-emitting diodes and / or one or more photodiodes.
[0015]
15. A method of light emission from an optoelectronic device (100) according to one of claims 1 to 13, comprising the implementation of a polarization of the optoelectronic device (100) by applying a voltage between the first electrode (s) (112) and the second electrode (116) of the optoelectronic device (100), and: - the application of a difference of electrical potentials between the at least one gate (118) or metal portion (154). ) and the one or more electrodes (112) electrically connected to the p-doped semiconductor portion (s) (106) such that the electrical potential applied to the at least one gate (118) or metal portion (154) is less than or equal to electric potential applied to the one or more electrodes (112) electrically connected to the p-doped semiconductor portion (s) (106), or - the application of a difference of electrical potentials between the at least one gate (118) or meta portions 1 and electrodes (112) electrically connected to the n-doped semiconductor portion (s) (106) such that the electrical potential applied to the at least one gate (118) or metal portion (154) is greater than or equal to the electrical potential applied to the one or more electrodes (112) electrically connected to the n-doped semiconductor portion (s) (106).
[0016]
16. A method of photoelectric conversion from an optoelectronic device (100) according to one of claims 1 to 13, comprising: - the application of a difference of electrical potentials between the grids (118) or metal portions (154) and the one or more electrodes (112) electrically connected to the p-doped semiconductor portion (s) (106) such that the electrical potential applied to the one or more grids (118) or metal portions (154) is less than or equal to the electrical potential applied to the one or more electrodes (112) electrically connected to the p-doped semiconductor portion (s) (106), or - the application of a difference in electrical potentials between the one or more grids (118) or metal portions (154) and the at least one electrodes (112) electrically connected to the at least one n-doped semiconductor portion (106) such that the electrical potential applied to the at least one gate (118) or metal portion (15). 4) is greater than or equal to the electrical potential applied to the at least one electrode (112) electrically connected to the at least one n-doped semiconductor portion (106).
[0017]
17. A method of producing an optoelectronic device (100) comprising at least the steps of: - producing a stack of layers comprising at least a first semiconductor layer (115) arranged between a second semiconductor layer (111) and an electrically conductive layer, one (115) of the first and second semiconductor layers being p-doped and the other (111) of the first and second semiconductor layers being p-doped. etching the stack of layers, providing at least one mena structure (124) comprising a first (106) and a second (108) semiconductor portion forming a pn junction and a first electrode (112) electrically connected to the first semiconductor portion (106), - producing an element (118, 120, 154) capable of ionizing dopants of the pn junction via a generation of an electric field in the pn junction and covering at least one part of fla lateral edges of at least a portion of the first (106) and / or the second (108) semi-conductor portion located at the pn junction; - producing a second electrode (116) electrically connected to the second semiconductor portion (108), and wherein at least the realization of the second electrode (116) comprises a planarization step of an electrically conductive material such as upper faces of at least the first electrode (112) and the second electrode (116) form a substantially planar continuous surface (122).

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2016-01-01| PLSC| Publication of the preliminary search report|Effective date: 20160101 |

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2017-06-30| PLFP| Fee payment|Year of fee payment: 4 |

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优先权:

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申请号 | 申请日 | 专利标题

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FR1456084A|FR3023065B1|2014-06-27|2014-06-27|P-N JUNCTION OPTOELECTRONIC DEVICE FOR IONIZATION OF FIELD EFFECT DOPANTS|FR1456084A| FR3023065B1|2014-06-27|2014-06-27|P-N JUNCTION OPTOELECTRONIC DEVICE FOR IONIZATION OF FIELD EFFECT DOPANTS|

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EP15173554.5A| EP2960951B1|2014-06-27|2015-06-24|Optoelectronic device with p-n junction enabling the ionisation of dopants by field effect|

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US14/750,156| US9601542B2|2014-06-27|2015-06-25|P-N junction optoelectronic device for ionizing dopants by field effect|

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KR1020150092502A| KR102357920B1|2014-06-27|2015-06-29|A p-n junction optoelectronic device for ionizing dopants by field effect|